Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices
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چکیده
During FPGA configuration, the error detection CRC feature detects configuration bitstream corruption when the bitstream is transferred from an external device into the FPGA. In user mode, the error detection CRC feature detects a single event upset (SEU) and determines the error type and location. In addition, Arria V, Cyclone V, and Stratix V devices support internal scrubbing, an ability to correct errors detected in user mode.
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